| dc.contributor.author | Andrade, Diego | |
| dc.contributor.author | Fraguela, Basilio B. | |
| dc.contributor.author | Doallo, Ramón | |
| dc.date.accessioned | 2023-11-30T15:35:48Z | |
| dc.date.available | 2023-11-30T15:35:48Z | |
| dc.date.issued | 2018 | |
| dc.identifier.citation | Andrade, D., Fraguela, B.B., Doallo, R. (2018). Guiding the Optimization of Parallel Codes on Multicores Using an Analytical Cache Model. In: Shi, Y., et al. Computational Science – ICCS 2018. ICCS 2018. Lecture Notes in Computer Science(), vol 10862. Springer, Cham. https://doi.org/10.1007/978-3-319-93713-7_32 | es_ES |
| dc.identifier.uri | http://hdl.handle.net/2183/34393 | |
| dc.description | Versión final aceptada de: https://doi.org/10.1007/978-3-319-93713-7_32 | es_ES |
| dc.description | This is a post-peer-review, pre-copyedit version of an article published in Lecture Notes
on Computer Science (ICCS 2018 proceedings). The final authenticated version is available
online at: http://dx.doi.org/10.1007/978-3-319-93713-7_32 | es_ES |
| dc.description.abstract | [Abstract]:
Cache performance is particularly hard to predict in modern multicore processors as several threads can be concurrently in execution, and private cache levels are combined with shared ones. This paper presents an analytical model able to evaluate the cache performance of the whole cache hierarchy for parallel applications in less than one second taking as input their source code and the cache configuration. While the model does not tackle some advanced hardware features, it can help optimizers to make reasonably good decisions in a very short time. This is supported by an evaluation based on two modern architectures and three different case studies, in which the model predictions differ on average just 5.05% from the results of a detailed hardware simulator and correctly guide different optimization decisions. | es_ES |
| dc.description.sponsorship | This research was supported by the Ministry of Economy and Competitiveness of Spain and FEDER funds (80%) of the EU (TIN2016-75845-P), and by the Government of Galicia (Xunta de Galicia) co-founded by the European Regional Development Fund (ERDF) under the Consolidation Programme of Competitive Reference Groups (ED431C 2017/04) as well as under the Centro Singular de Investigación de Galicia accreditation 2016-2019 (ED431G/01). We also acknowledge the Centro de Supercomputación de Galicia (CESGA) for the use of their computers. | es_ES |
| dc.description.sponsorship | Xunta de Galicia; ED431C 2017/04 | es_ES |
| dc.description.sponsorship | Xunta de Galicia; ED431G/01 | es_ES |
| dc.language.iso | eng | es_ES |
| dc.relation | info:eu-repo/grantAgreement/MINECO/Plan Estatal de Investigación Científica y Técnica y de Innovación 2013-2016/TIN2016-75845-P/ES/NUEVOS DESAFIOS EN COMPUTACION DE ALTAS PRESTACIONES: DESDE ARQUITECTURAS HASTA APLICACIONES (II)/ | es_ES |
| dc.relation.isversionof | https://doi.org/10.1007/978-3-319-93713-7_32 | |
| dc.relation.uri | https://doi.org/10.1007/978-3-319-93713-7_32 | es_ES |
| dc.rights | Todos os dereitos reservados. All rights reserved. | es_ES |
| dc.subject | Analytical Cache Model | es_ES |
| dc.subject | Multicore processors | es_ES |
| dc.subject | Cache performance | es_ES |
| dc.subject | Optimization | es_ES |
| dc.title | Guiding the Optimization of Parallel Codes on Multicores Using an Analytical Cache Model | es_ES |
| dc.type | info:eu-repo/semantics/conferenceObject | es_ES |
| dc.type | info:eu-repo/semantics/conferenceObject | es_ES |
| dc.rights.access | info:eu-repo/semantics/openAccess | es_ES |
| dc.identifier.doi | 10.1007/978-3-319-93713-7_32 | |
| UDC.coleccion | Investigación | |
| UDC.departamento | Enxeñaría de Computadores | |
| UDC.grupoInv | Grupo de Arquitectura de Computadores (GAC) | |
