Mostrar o rexistro simple do ítem

dc.contributor.authorKommrusch, Steve
dc.contributor.authorHorro, Marcos
dc.contributor.authorPouchet, Louis-Noël
dc.contributor.authorRodríguez, Gabriel
dc.contributor.authorTouriño, Juan
dc.date.accessioned2021-04-15T14:32:22Z
dc.date.available2021-04-15T14:32:22Z
dc.date.issued2021-02-09
dc.identifier.citationS. Kommrusch, M. Horro, L. -N. Pouchet, G. Rodríguez and J. Touriño, "Optimizing Coherence Traffic in Manycore Processors Using Closed-Form Caching/Home Agent Mappings," in IEEE Access, vol. 9, pp. 28930-28945, 2021, doi: 10.1109/ACCESS.2021.3058280.es_ES
dc.identifier.issn2169-3536
dc.identifier.urihttp://hdl.handle.net/2183/27758
dc.description.abstract[Abstract] Manycore processors feature a high number of general-purpose cores designed to work in a multithreaded fashion. Recent manycore processors are kept coherent using scalable distributed directories. A paramount example is the Intel Mesh interconnect, which consists of a network-on-chip interconnecting “tiles”, each of which contains computation cores, local caches, and coherence masters. The distributed coherence subsystem must be queried for every out-of-tile access, imposing an overhead on memory latency. This paper studies the physical layout of an Intel Knights Landing processor, with a particular focus on the coherence subsystem, and uncovers the pseudo-random mapping function of physical memory blocks across the pieces of the distributed directory. Leveraging this knowledge, candidate optimizations to improve memory latency through the minimization of coherence traffic are studied. Although these optimizations do improve memory throughput, ultimately this does not translate into performance gains due to inherent overheads stemming from the computational complexity of the mapping functions.es_ES
dc.description.sponsorshipMinisterio de Educación; FPU16/00816es_ES
dc.description.sponsorshipU.S. National Science Foundation; CCF-1750399es_ES
dc.description.sponsorshipXunta de Galicia and FEDER; ED431G 2019/01es_ES
dc.description.sponsorshipMinisterio de Ciencia e Innovación; PID2019-104184RB-I00es_ES
dc.language.isoenges_ES
dc.publisherInstitute of Electrical and Electronics Engineerses_ES
dc.relation.urihttps://doi.org/10.1109/ACCESS.2021.3058280es_ES
dc.rightsAtribución 3.0 Españaes_ES
dc.rights.urihttp://creativecommons.org/licenses/by/3.0/es/*
dc.subjectCoherencees_ES
dc.subjectLayoutes_ES
dc.subjectOptimizationes_ES
dc.subjectManycore processorses_ES
dc.subjectDynamic schedulinges_ES
dc.subjectTask analysises_ES
dc.subjectStandardses_ES
dc.titleOptimizing Coherence Traffic in Manycore Processors Using Closed-Form Caching/Home Agent Mappingses_ES
dc.typeinfo:eu-repo/semantics/articlees_ES
dc.rights.accessinfo:eu-repo/semantics/openAccesses_ES
UDC.journalTitleIEEE Accesses_ES
UDC.volume9es_ES
UDC.startPage28930es_ES
UDC.endPage28945es_ES
dc.identifier.doi10.1109/ACCESS.2021.3058280.


Ficheiros no ítem

Thumbnail
Thumbnail

Este ítem aparece na(s) seguinte(s) colección(s)

Mostrar o rexistro simple do ítem