Optimizing Coherence Traffic in Manycore Processors Using Closed-Form Caching/Home Agent Mappings

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http://hdl.handle.net/2183/27758Collections
- Investigación (FIC) [1618]
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Optimizing Coherence Traffic in Manycore Processors Using Closed-Form Caching/Home Agent MappingsDate
2021-02-09Citation
S. Kommrusch, M. Horro, L. -N. Pouchet, G. Rodríguez and J. Touriño, "Optimizing Coherence Traffic in Manycore Processors Using Closed-Form Caching/Home Agent Mappings," in IEEE Access, vol. 9, pp. 28930-28945, 2021, doi: 10.1109/ACCESS.2021.3058280.
Abstract
[Abstract]
Manycore processors feature a high number of general-purpose cores designed to work in a multithreaded fashion. Recent manycore processors are kept coherent using scalable distributed directories. A paramount example is the Intel Mesh interconnect, which consists of a network-on-chip interconnecting “tiles”, each of which contains computation cores, local caches, and coherence masters. The distributed coherence subsystem must be queried for every out-of-tile access, imposing an overhead on memory latency. This paper studies the physical layout of an Intel Knights Landing processor, with a particular focus on the coherence subsystem, and uncovers the pseudo-random mapping function of physical memory blocks across the pieces of the distributed directory. Leveraging this knowledge, candidate optimizations to improve memory latency through the minimization of coherence traffic are studied. Although these optimizations do improve memory throughput, ultimately this does not translate into performance gains due to inherent overheads stemming from the computational complexity of the mapping functions.
Keywords
Coherence
Layout
Optimization
Manycore processors
Dynamic scheduling
Task analysis
Standards
Layout
Optimization
Manycore processors
Dynamic scheduling
Task analysis
Standards
Editor version
Rights
Atribución 3.0 España
ISSN
2169-3536