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dc.contributor.authorCereijo García, Javier
dc.contributor.authorOsorio, Roberto
dc.date.accessioned2021-02-24T15:37:23Z
dc.date.available2021-02-24T15:37:23Z
dc.date.issued2020-01-16
dc.identifier.citationJ. C. García and R. R. Osorio, "Hardware Implementation of Statecharts for FPGA-based Control in Scientific Facilities," 2019 XXXIV Conference on Design of Circuits and Integrated Systems (DCIS), Bilbao, Spain, 2019, pp. 1-6, doi: 10.1109/DCIS201949030.2019.8959871es_ES
dc.identifier.urihttp://hdl.handle.net/2183/27369
dc.descriptionDate of Conference: 20-22 Nov. 2019; Conference Location: Bilbao, Spaines_ES
dc.description.abstract[Abstract] The problem of generating complex synchronization patterns using automated tools is addressed in this paper. This work was originally motivated by the need of fast and jitter free synchronization in scientific facilities, where a large number of sensors and actuators must be controlled at the right time in a variety of situations. Programmable processors cannot meet the real-time requirements, forcing to use dedicated circuits to produce and transmit the control signals. Designing application specific hardware by hand is a slow and error-prone task. Hence, a set of tools is required that allow specifying the control systems in a clear and efficient way and producing synthesizable HDL (hardware description language) code in an automated manner. Statechart diagrams have been selected as the input method, and this work focuses on how to translate those diagrams into HDL code. We present a tool that analyzes a Statecharts specification and implements the required control systems using FPGAs. A number of solutions are provided to deal with multiple triggering events and concurrent super-states. Also, an alternative microprogrammed implementation is proposed.es_ES
dc.description.sponsorshipThis work was funded in part by the Ministry of Economy and Competitiveness of Spain, Project TIN2016-75845-P (AEI/FEDER, UE), Xunta de Galicia and FEDER funds of the EU under the Consolidation Program of Competitive Reference Groups (ED431C 2017/04), and under the Centro Singular de Investigaci ´on de Galicia accreditation 2016-2019 (ED431G/01)es_ES
dc.description.sponsorshipXunta de Galicia; ED431C 2017/04es_ES
dc.description.sponsorshipXunta de Galicia; ED431G/01es_ES
dc.language.isoenges_ES
dc.publisherInstitute of Electrical and Electronics Engineerses_ES
dc.relationinfo:eu-repo/grantAgreement/MINECO/Plan Estatal de Investigación Científica y Técnica y de Innovación 2013-2016/TIN2016-75845-P/ES/NUEVOS DESAFIOS EN COMPUTACION DE ALTAS PRESTACIONES: DESDE ARQUITECTURAS HASTA APLICACIONES (II)/
dc.relation.urihttps://doi.org/10.1109/DCIS201949030.2019.8959871es_ES
dc.rights© 2020 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.es_ES
dc.subjectToolses_ES
dc.subjectHistoryes_ES
dc.subjectTiminges_ES
dc.subjectXMLes_ES
dc.subjectReceiverses_ES
dc.subjectHardware design languageses_ES
dc.subjectHardwarees_ES
dc.titleHardware Implementation of Statecharts for FPGA-based Control in Scientific Facilitieses_ES
dc.typeinfo:eu-repo/semantics/conferenceObjectes_ES
dc.rights.accessinfo:eu-repo/semantics/openAccesses_ES
UDC.startPage1es_ES
UDC.endPage6es_ES
UDC.conferenceTitlePopular 2019 XXXIV Conference on Design of Circuits and Integrated Systems (DCIS)es_ES


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