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Hardware Implementation of Statecharts for FPGA-based Control in Scientific Facilities
dc.contributor.author | Cereijo García, Javier | |
dc.contributor.author | Osorio, Roberto | |
dc.date.accessioned | 2021-02-24T15:37:23Z | |
dc.date.available | 2021-02-24T15:37:23Z | |
dc.date.issued | 2020-01-16 | |
dc.identifier.citation | J. C. García and R. R. Osorio, "Hardware Implementation of Statecharts for FPGA-based Control in Scientific Facilities," 2019 XXXIV Conference on Design of Circuits and Integrated Systems (DCIS), Bilbao, Spain, 2019, pp. 1-6, doi: 10.1109/DCIS201949030.2019.8959871 | es_ES |
dc.identifier.uri | http://hdl.handle.net/2183/27369 | |
dc.description | Date of Conference: 20-22 Nov. 2019; Conference Location: Bilbao, Spain | es_ES |
dc.description.abstract | [Abstract] The problem of generating complex synchronization patterns using automated tools is addressed in this paper. This work was originally motivated by the need of fast and jitter free synchronization in scientific facilities, where a large number of sensors and actuators must be controlled at the right time in a variety of situations. Programmable processors cannot meet the real-time requirements, forcing to use dedicated circuits to produce and transmit the control signals. Designing application specific hardware by hand is a slow and error-prone task. Hence, a set of tools is required that allow specifying the control systems in a clear and efficient way and producing synthesizable HDL (hardware description language) code in an automated manner. Statechart diagrams have been selected as the input method, and this work focuses on how to translate those diagrams into HDL code. We present a tool that analyzes a Statecharts specification and implements the required control systems using FPGAs. A number of solutions are provided to deal with multiple triggering events and concurrent super-states. Also, an alternative microprogrammed implementation is proposed. | es_ES |
dc.description.sponsorship | This work was funded in part by the Ministry of Economy and Competitiveness of Spain, Project TIN2016-75845-P (AEI/FEDER, UE), Xunta de Galicia and FEDER funds of the EU under the Consolidation Program of Competitive Reference Groups (ED431C 2017/04), and under the Centro Singular de Investigaci ´on de Galicia accreditation 2016-2019 (ED431G/01) | es_ES |
dc.description.sponsorship | Xunta de Galicia; ED431C 2017/04 | es_ES |
dc.description.sponsorship | Xunta de Galicia; ED431G/01 | es_ES |
dc.language.iso | eng | es_ES |
dc.publisher | Institute of Electrical and Electronics Engineers | es_ES |
dc.relation | info:eu-repo/grantAgreement/MINECO/Plan Estatal de Investigación Científica y Técnica y de Innovación 2013-2016/TIN2016-75845-P/ES/NUEVOS DESAFIOS EN COMPUTACION DE ALTAS PRESTACIONES: DESDE ARQUITECTURAS HASTA APLICACIONES (II)/ | |
dc.relation.uri | https://doi.org/10.1109/DCIS201949030.2019.8959871 | es_ES |
dc.rights | © 2020 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. | es_ES |
dc.subject | Tools | es_ES |
dc.subject | History | es_ES |
dc.subject | Timing | es_ES |
dc.subject | XML | es_ES |
dc.subject | Receivers | es_ES |
dc.subject | Hardware design languages | es_ES |
dc.subject | Hardware | es_ES |
dc.title | Hardware Implementation of Statecharts for FPGA-based Control in Scientific Facilities | es_ES |
dc.type | info:eu-repo/semantics/conferenceObject | es_ES |
dc.rights.access | info:eu-repo/semantics/openAccess | es_ES |
UDC.startPage | 1 | es_ES |
UDC.endPage | 6 | es_ES |
UDC.conferenceTitle | Popular 2019 XXXIV Conference on Design of Circuits and Integrated Systems (DCIS) | es_ES |