Mostrar o rexistro simple do ítem
Truncated SIMD Multiplier Architecture for Approximate Computing in Low-Power Programmable Processors
dc.contributor.author | Osorio, Roberto | |
dc.contributor.author | Rodríguez, Gabriel | |
dc.date.accessioned | 2024-01-12T20:04:48Z | |
dc.date.available | 2024-01-12T20:04:48Z | |
dc.date.issued | 2019 | |
dc.identifier.citation | R. R. Osorio and G. Rodríguez, "Truncated SIMD Multiplier Architecture for Approximate Computing in Low-Power Programmable Processors," in IEEE Access, vol. 7, pp. 56353-56366, 2019, doi: 10.1109/ACCESS.2019.2913743. | es_ES |
dc.identifier.issn | 2169-3536 | |
dc.identifier.uri | http://hdl.handle.net/2183/34895 | |
dc.description.abstract | [Abstract]: Approximate computing has been exploited for many years in application-specific architectures. Recently, it has also been proposed for low-power programmable processors. However, this poses some challenges as, in a microprocessor, the energy consumed by fetching and decoding an instruction may be significantly higher than that of the execution itself. Therefore, approximate computing would be advisable only for those instructions, in which the execution stage is significantly expensive in terms of energy consumption. In this paper, we present new architectures for truncated SIMD multipliers able to calculate signed and unsigned products from 8 × 8 to 64× 64 bits. Next, we analyze the precision loss incurred by truncation for all product sizes. We implement accurate and truncated architectures for both scalar and SIMD products and find that truncation allows area savings of up to 27%. The proposed design is experimentally evaluated in different scenarios, showing potential energy savings ranging from 29% to 42%. Finally, this paper analyzes the overall convenience of introducing truncated SIMD architectures with respect to accurate SIMD and scalar architectures. | es_ES |
dc.description.sponsorship | This work was supported in part by the Ministry of Economy and Competitiveness of Spain under Project TIN2016-75845-P (AEI/FEDER, UE), in part by the Xunta de Galicia and FEDER Funds of the EU under the Consolidation Program of Competitive Reference Groups under Grant ED431C 2017/04, and in part by the Centro Singular de Investigación de Galicia Accreditation 2016 2019 under Grant ED431G/01. | es_ES |
dc.description.sponsorship | Xunta de Galicia; ED431C 2017/04 | es_ES |
dc.description.sponsorship | Xunta de Galicia; ED431G/01 | es_ES |
dc.language.iso | eng | es_ES |
dc.publisher | Institute of Electrical and Electronics Engineers | es_ES |
dc.relation | info:eu-repo/grantAgreement/MINECO/Plan Estatal de Investigación Científica y Técnica y de Innovación 2013-2016/TIN2016-75845-P/ES/NUEVOS DESAFIOS EN COMPUTACION DE ALTAS PRESTACIONES: DESDE ARQUITECTURAS HASTA APLICACIONES (II)/ | es_ES |
dc.relation.uri | https://doi.org/10.1109/ACCESS.2019.2913743 | es_ES |
dc.rights | Atribución-NoComercial-SinDerivadas 4.0 Internacional ( CC-BY-NC-ND) | es_ES |
dc.rights.uri | https://creativecommons.org/licenses/by-nc-nd/4.0/deed.es | |
dc.subject | Digital arithmetic | es_ES |
dc.subject | Fixed-point arithmetic | es_ES |
dc.subject | Approximate computing | es_ES |
dc.subject | Approximate multiplier | es_ES |
dc.subject | Low power | es_ES |
dc.title | Truncated SIMD Multiplier Architecture for Approximate Computing in Low-Power Programmable Processors | es_ES |
dc.type | info:eu-repo/semantics/article | es_ES |
dc.rights.access | info:eu-repo/semantics/openAccess | es_ES |
UDC.journalTitle | IEEE Access | es_ES |
UDC.volume | 7 | es_ES |
UDC.startPage | 56353 | es_ES |
UDC.endPage | 56366 | es_ES |
dc.identifier.doi | 10.1109/ACCESS.2019.2913743 |
Ficheiros no ítem
Este ítem aparece na(s) seguinte(s) colección(s)
-
GI-GAC - Artigos [187]