High-Speed FPGA Architecture for CABAC Decoding Acceleration in H.264/AVC Standard
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TitleHigh-Speed FPGA Architecture for CABAC Decoding Acceleration in H.264/AVC Standard
Osorio, R.R. & Bruguera, J.D. J Sign Process Syst (2013) 72: 119. https://doi.org/10.1007/s11265-012-0718-y
[Abstract] Video encoding and decoding are computing intensive applications that require high performance processors or dedicated hardware. Video decoding offers a high parallel processing potential that may be exploited. However, a particular task challenges parallelization: entropy decoding. In H.264 and SVC video standards, this task is mainly carried out using arithmetic decoding, an strictly sequential algorithm that achieves results close to the entropy limit. By accelerating arithmetic decoding, the bottleneck is removed and parallel decoding is enabled. Many works have been published on accelerating pure binary encoding and decoding. However, little research has been done into how to integrate binary decoding with context managing and control without losing performance. In this work we propose a FPGA-based architecture that achieves real time decoding for high-definition video by sustaining a 1 bin per cycle throughput. This is accomplished by implementing fast bin decoding; a novel and area efficient context-managing mechanism; and optimized control scheduling.
This is a post-peer-review, pre-copyedit version of an article published in Journal of Signal Processing Systems. The final authenticated version is available online at: https://doi.org/10.1007/s11265-012-0718-y.