Comparison of Hardwired and Microprogrammed Statechart Implementations

UDC.coleccionInvestigaciónes_ES
UDC.departamentoEnxeñaría de Computadoreses_ES
UDC.grupoInvGrupo de Arquitectura de Computadores (GAC)es_ES
UDC.issue7es_ES
UDC.journalTitleElectronicses_ES
UDC.startPage1139es_ES
UDC.volume9es_ES
dc.contributor.authorCereijo García, Javier
dc.contributor.authorOsorio, Roberto
dc.date.accessioned2024-01-12T19:40:48Z
dc.date.available2024-01-12T19:40:48Z
dc.date.issued2020
dc.description.abstract[Abstract]: In scientific facilities such as particle accelerators, fast and jitter-free synchronization is required in order to trigger a large number of actuators at the right time in a variety of situations. The behaviour of the control systems and subsystems may be specified by using statechart diagrams, which expand the capabilities of finite state machines allowing concurrency, a hierarchy of states, and history. Hence, there is a need of tools for synthesizing those diagrams so that a new control configuration may be deployed in a short time and an error-free manner in the required environments. In this work, we present a tool that analyses the specification of a variant of the State Chart XML (SCXML) standard tailored to hardware systems and produces a hardware description language (HDL) code suited to implement the required control systems using FPGAs. A number of solutions are provided to deal with the specific features of statecharts, such as multiple triggering events and concurrent super-states. We also present a microprogrammed architecture able to implement statecharts defined as firmware. Finally, we compare the advantages of each strategy in terms of usability, resource usage, and performance, and their applicability to a specific facility is evaluated.es_ES
dc.description.sponsorshipThis research was funded in part by the Ministry of Science and Innovation of Spain (project TIN2016-75845-P, AEI/FEDER/EU), Xunta de Galicia and FEDER funds of the EU under the Consolidation Program of Competitive Reference Groups (ED431C 2017/04), and under the Centro de Investigación de Galicia accreditation 2019-2022 (ED431G 2019/01).es_ES
dc.description.sponsorshipXunta de Galicia; ED431C 2017/04es_ES
dc.description.sponsorshipXunta de Galicia; ED431G 2019/01es_ES
dc.identifier.citationCereijo García, J.; Osorio, R.R. Comparison of Hardwired and Microprogrammed Statechart Implementations. Electronics 2020, 9, 1139. https://doi.org/10.3390/electronics9071139es_ES
dc.identifier.doi10.3390/electronics9071139
dc.identifier.issn2079-9292
dc.identifier.urihttp://hdl.handle.net/2183/34894
dc.language.isoenges_ES
dc.publisherMDPIes_ES
dc.relation.projectIDinfo:eu-repo/grantAgreement/MINECO/Plan Estatal de Investigación Científica y Técnica y de Innovación 2013-2016/TIN2016-75845-P/ES/NUEVOS DESAFIOS EN COMPUTACION DE ALTAS PRESTACIONES: DESDE ARQUITECTURAS HASTA APLICACIONES (II)/es_ES
dc.relation.urihttps://doi.org/10.3390/electronics9071139es_ES
dc.rightsAtribución 4.0 Internacionales_ES
dc.rights.accessRightsopen accesses_ES
dc.rights.urihttp://creativecommons.org/licenses/by/3.0/es/*
dc.subjectStatechartses_ES
dc.subjectFinite state machineses_ES
dc.subjectIndustrial controles_ES
dc.subjectFPGAes_ES
dc.titleComparison of Hardwired and Microprogrammed Statechart Implementationses_ES
dc.typejournal articlees_ES
dspace.entity.typePublication
relation.isAuthorOfPublicationeac2943b-5be2-46e9-9816-09ae10df6b76
relation.isAuthorOfPublication.latestForDiscoveryeac2943b-5be2-46e9-9816-09ae10df6b76

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