Formal Verification of Source-to-Source Transformations for HLS

UDC.coleccionInvestigaciónes_ES
UDC.conferenceTitleFPGA 2024es_ES
UDC.departamentoEnxeñaría de Computadoreses_ES
UDC.grupoInvGrupo de Arquitectura de Computadores (GAC)es_ES
dc.contributor.authorPouchet, Louis-Noël
dc.contributor.authorTucker, Emily
dc.contributor.authorZhang, Niansong
dc.contributor.authorChen, Hongzheng
dc.contributor.authorPal, Debjit
dc.contributor.authorRodríguez, Gabriel
dc.contributor.authorZhang, Zhiru
dc.date.accessioned2024-09-30T08:06:32Z
dc.date.available2024-09-30T08:06:32Z
dc.date.issued2024
dc.descriptionPresented at: 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA '24)es_ES
dc.description.abstract[Abstract]: High-level synthesis (HLS) can greatly facilitate the description of complex hardware implementations, by raising the level of abstraction up to a classical imperative language such as C/C++, usually augmented with vendor-specific pragmas and APIs. Despite productivity improvements, attaining high performance for the final design remains a challenge, and higher-level tools like source-to-source compilers have been developed to generate programs targeting HLS toolchains. These tools may generate highly complex HLS-ready C/C++ code, reducing the programming effort and enabling critical optimizations. However, whether these HLS-friendly programs are produced by a human or a tool, validating their correctness or exposing bugs otherwise remains a fundamental challenge. In this work we target the problem of efficiently checking the semantics equivalence between two programs written in C/C++ as a means to ensuring the correctness of the description provided to the HLS toolchain, by proving an optimized code version fully preserves the semantics of the unoptimized one. We introduce a novel formal verification approach that combines concrete and abstract interpretation with a hybrid symbolic analysis. Notably, our approach is mostly agnostic to how control-flow, data storage, and dataflow are implemented in the two programs. It can prove equivalence under complex bufferization and loop/syntax transformations, for a rich class of programs with statically interpretable control-flow. We present our techniques and their complete end-to-end implementation, demonstrating how our system can verify the correctness of highly complex programs generated by source-to-source compilers for HLS, and detect bugs that may elude co-simulation.es_ES
dc.description.sponsorshipThis work was supported in part by an Intel ISRA award; U.S. NSF awards #1750399 and #2019306; ACE, one of seven centers in JUMP 2.0, an SRC program sponsored by DARPA; and Grant PID2022-136435NB-I00, funded by MCIN/AEI/10.13039/501100011033 and by "ERDF A way of making Europe", EU. We are particularly thankful to Jin Yang, Jeremy Casas, and Zhenkun Yang from Intel for their support and guidance on the ISRA project. We also thank Lana Josipovi and the anonymous reviewers for their feedback on earlier versions of this manuscript.es_ES
dc.description.sponsorshipUnited States. National Science Foundation; 1750399es_ES
dc.description.sponsorshipUnited States. National Science Foundation; 2019306es_ES
dc.identifier.citationLouis-Noël Pouchet, Emily Tucker, Niansong Zhang, Hongzheng Chen, Debjit Pal, Gabriel Rodríguez, and Zhiru Zhang. 2024. Formal Verification of Source-to-Source Transformations for HLS. In Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA '24). Association for Computing Machinery, New York, NY, USA, 97–107. https://doi.org/10.1145/3626202.3637563es_ES
dc.identifier.doi10.1145/3626202.3637563
dc.identifier.urihttp://hdl.handle.net/2183/39269
dc.language.isoenges_ES
dc.publisherAssociation for Computing Machinery, Inces_ES
dc.relation.projectIDinfo:eu-repo/grantAgreement/AEI/Plan Estatal de Investigación Científica y Técnica y de Innovación 2021-2023/PID2022-136435NB-I00/ES/ARQUITECTURAS, FRAMEWORKS Y APLICACIONES DE LA COMPUTACION DE ALTAS PRESTACIONESes_ES
dc.relation.urihttps://doi.org/10.1145/3626202.3637563es_ES
dc.rights© 2024 Copyright held by the owner/author(s).es_ES
dc.rights.accessRightsopen accesses_ES
dc.subjectFormal verificationes_ES
dc.subjectHigh-level synthesises_ES
dc.subjectProgram equivalencees_ES
dc.titleFormal Verification of Source-to-Source Transformations for HLSes_ES
dc.typeconference outputes_ES
dspace.entity.typePublication
relation.isAuthorOfPublicatione432b4b1-5ead-41aa-b165-d69608b06626
relation.isAuthorOfPublication.latestForDiscoverye432b4b1-5ead-41aa-b165-d69608b06626

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