Floating Point Calculation of the Cube Function on FPGAs

Bibliographic citation

R. R. Osorio, "Floating Point Calculation of the Cube Function on FPGAs," in IEEE Transactions on Parallel and Distributed Systems, vol. 34, no. 1, pp. 372-382, 1 Jan. 2023, doi: 10.1109/TPDS.2022.3220039.

Type of academic work

Academic degree

Abstract

[Abstract]: Specialized arithmetic units allow fast and efficient computation of lesser used mathematical functions. The overall impact of those units would be negligible in a general purpose processor, as added circuitry makes chips more complex despite most software would seldom make use of it. On the opposite side, custom computing machines are built for a specific task, and they can always benefit from specialized units if they are available. In this work, floating point architectures are proposed for computing the cube on Intel and Xilinx FPGAs. Those implementations reduce the cost and latency compared to using simple floating point multiplications and squarers.

Description

© 2023 IEEE. This version of the paper has been accepted for publication. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The final published paper is available online at: https://doi.org/10.1109/TPDS.2022.3220039

Rights

© 2023, IEEE. Todos os dereitos reservados. All right reserved.