dc.contributor.author | Castro, Manuel de | |
dc.contributor.author | Osorio, Roberto | |
dc.contributor.author | López Vilariño, David | |
dc.contributor.author | González-Escribano, Arturo | |
dc.contributor.author | Llanos, Diego R. | |
dc.date.accessioned | 2023-03-29T09:11:52Z | |
dc.date.available | 2023-03-29T09:11:52Z | |
dc.date.issued | 2023 | |
dc.identifier.citation | M. de Castro, R.R. Osorio, D.L. Vilariño, A. González-Escribano, Diego R. Llanos, "Implementation of a motion estimation algorithm for Intel FPGAs using OpenCL", Journal of Supercomputing, 2023 [Online]. doi: 10.1007/s11227-023-05051-3, Disponible en: https://doi.org/10.1007/s11227-023-05051-3 | es_ES |
dc.identifier.uri | http://hdl.handle.net/2183/32803 | |
dc.description | Financiado para publicación en acceso aberto: CRUE-CSIC | es_ES |
dc.description.abstract | [Abstract]: Motion Estimation is one of the main tasks behind any video encoder. It is a computationally costly task; therefore, it is usually delegated to specific or reconfigurable hardware, such as FPGAs. Over the years, multiple FPGA implementations have been developed, mainly using hardware description languages such as Verilog or VHDL. Since programming using hardware description languages is a complex task, it is desirable to use higher-level languages to develop FPGA applications.The aim of this work is to evaluate OpenCL, in terms of expressiveness, as a tool for developing this kind of FPGA applications. To do so, we present and evaluate a parallel implementation of the Block Matching Motion Estimation process using OpenCL for Intel FPGAs, usable and tested on an Intel Stratix 10 FPGA. The implementation efficiently processes Full HD frames completely inside the FPGA. In this work, we show the resource utilization when synthesizing the code on an Intel Stratix 10 FPGA, as well as a performance comparison with multiple CPU implementations with varying levels of optimization and vectorization capabilities. We also compare the proposed OpenCL implementation, in terms of resource utilization and performance, with estimations obtained from an equivalent VHDL implementation. | es_ES |
dc.description.sponsorship | Junta de Castilla y León; VA226P20 | es_ES |
dc.description.sponsorship | Xunta de Galicia; ED431G 2019/01 | es_ES |
dc.description.sponsorship | Xunta de Galicia; ED431C 2021/30 | es_ES |
dc.description.sponsorship | This work has been funded by the Consejería de Educación of Junta de Castilla y León, Project PROPHET-2 (VA226P20), and Ministerio de Economía, Industria y Competitividad of Spain, European Regional Development Fund (ERDF) program: Project PCAS (TIN2017-88614-R). David L. Vilariño is funded by Ministerio de Economía, Industria y Competitividad of Spain (PID2019-104834 GB-I00). Roberto R. Osorio is funded by the Ministry of Science and Innovation of Spain (PID2019-104184RB-I00 / AEI / 10.13039/501100011033), and by Xunta de Galicia and FEDER funds of the EU (Centro de Investigacion de Galicia accreditation 2019-2022, ref. ED431G 2019/01; Consolidation Program of Competitive Reference Groups, ref. ED431C 2021/30). This work was also supported in part by grant TED2021-130367B-I00 funded by MCIN/AEI/10.13039/501100011033 and by “European Union NextGenerationEU/PRTR”. | es_ES |
dc.language.iso | eng | es_ES |
dc.publisher | Springer | es_ES |
dc.relation | info:eu-repo/grantAgreement/AEI/Plan Estatal de Investigación Científica y Técnica y de Innovación 2013-2016/TIN2017-88614-R/ES/ESPACIO DE DIRECCIONES PARTICIONADO, COMUNICADO Y ESCALABLE EN ENTORNOS HETEROGENEOS | es_ES |
dc.relation | info:eu-repo/grantAgreement/AEI/Plan Estatal de Investigación Científica y Técnica y de Innovación 2017-2020/PID2019-104834GB-I00/ES/COMPUTACION DE ALTAS PRESTACIONES Y CLOUD PARA APLICACIONES DE ALTO INTERES | es_ES |
dc.relation | info:eu-repo/grantAgreement/AEI/Plan Estatal de Investigación Científica y Técnica y de Innovación 2017-2020/PID2019-104184RB-I00/ES/DESAFIOS ACTUALES EN HPC: ARQUITECTURAS, SOFTWARE Y APLICACIONES | es_ES |
dc.relation | info:eu-repo/grantAgreement/AEI/Plan Estatal de Investigación Científica y Técnica y de Innovación 2021-2023/TED2021-130367B-I00/ES/Monitorización Dixital Rápida de Ecosistemas Fluviais | es_ES |
dc.relation.uri | https://doi.org/10.1007/s11227-023-05051-3 | es_ES |
dc.rights | Atribución 4.0 Internacional (CC BY 4.0) | es_ES |
dc.rights.uri | http://creativecommons.org/licenses/by/3.0/es/ | * |
dc.subject | FPGA | es_ES |
dc.subject | Motion estimation | es_ES |
dc.subject | OpenCL | es_ES |
dc.subject | Video coding | es_ES |
dc.title | Implementation of a motion estimation algorithm for Intel FPGAs using OpenCL | es_ES |
dc.type | info:eu-repo/semantics/article | es_ES |
dc.rights.access | info:eu-repo/semantics/openAccess | es_ES |
UDC.journalTitle | Journal of Supercomputing | es_ES |
dc.identifier.doi | 10.1007/s11227-023-05051-3 | |
UDC.coleccion | Investigación | |
UDC.departamento | Enxeñaría de Computadores | |
UDC.grupoInv | Grupo de Arquitectura de Computadores (GAC) | |