Mostrar o rexistro simple do ítem
Floating Point Calculation of the Cube Function on FPGAs
| dc.contributor.author | Osorio, Roberto | |
| dc.date.accessioned | 2024-01-15T09:29:32Z | |
| dc.date.available | 2024-01-15T09:29:32Z | |
| dc.date.issued | 2023 | |
| dc.identifier.citation | R. R. Osorio, "Floating Point Calculation of the Cube Function on FPGAs," in IEEE Transactions on Parallel and Distributed Systems, vol. 34, no. 1, pp. 372-382, 1 Jan. 2023, doi: 10.1109/TPDS.2022.3220039. | es_ES |
| dc.identifier.issn | 1045-9219 | |
| dc.identifier.issn | 1558-2183 | |
| dc.identifier.uri | http://hdl.handle.net/2183/34902 | |
| dc.description | © 2023 IEEE. This version of the paper has been accepted for publication. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The final published paper is available online at: https://doi.org/10.1109/TPDS.2022.3220039 | es_ES |
| dc.description.abstract | [Abstract]: Specialized arithmetic units allow fast and efficient computation of lesser used mathematical functions. The overall impact of those units would be negligible in a general purpose processor, as added circuitry makes chips more complex despite most software would seldom make use of it. On the opposite side, custom computing machines are built for a specific task, and they can always benefit from specialized units if they are available. In this work, floating point architectures are proposed for computing the cube on Intel and Xilinx FPGAs. Those implementations reduce the cost and latency compared to using simple floating point multiplications and squarers. | es_ES |
| dc.description.sponsorship | This work was supported by the Ministry of Science and Innovation of Spain (PID2019-104184RB-I00 / AEI / 10.13039/501100011033), and by Xunta de Galicia and FEDER funds of the EU (Centro de Investigaci´on de Galicia accreditation 2019–2022, ref. ED431G 2019/01; Consolidation Program of Competitive Reference Groups, ref. ED431C 2021/30). | es_ES |
| dc.description.sponsorship | Xunta de Galicia; ED431G 2019/01 | es_ES |
| dc.description.sponsorship | Xunta de Galicia; ED431C 2021/30 | es_ES |
| dc.language.iso | eng | es_ES |
| dc.publisher | Institute of Electrical and Electronics Engineers | es_ES |
| dc.relation | info:eu-repo/grantAgreement/AEI/Plan Estatal de Investigación Científica y Técnica y de Innovación 2017-2020/PID2019-104184RB-I00/ES/DESAFIOS ACTUALES EN HPC: ARQUITECTURAS, SOFTWARE Y APLICACIONES | es_ES |
| dc.relation.isversionof | https://doi.org/10.1109/TPDS.2022.3220039 | |
| dc.relation.uri | https://doi.org/10.1109/TPDS.2022.3220039 | es_ES |
| dc.rights | © 2023, IEEE. Todos os dereitos reservados. All right reserved. | es_ES |
| dc.subject | Floating-point arithmetic | es_ES |
| dc.subject | Numerical analysis | es_ES |
| dc.subject | Field programmable gate arrays | es_ES |
| dc.subject | Digital integrated circuits | es_ES |
| dc.title | Floating Point Calculation of the Cube Function on FPGAs | es_ES |
| dc.type | info:eu-repo/semantics/article | es_ES |
| dc.rights.access | info:eu-repo/semantics/openAccess | es_ES |
| UDC.journalTitle | IEEE Transactions on Parallel and Distributed Systems | es_ES |
| UDC.volume | 34 | es_ES |
| UDC.issue | 1 | es_ES |
| UDC.startPage | 372 | es_ES |
| UDC.endPage | 382 | es_ES |
| dc.identifier.doi | 10.1109/TPDS.2022.3220039 |
Ficheiros no ítem
Este ítem aparece na(s) seguinte(s) colección(s)
-
GI-GAC - Artigos [181]
