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Mostrando ítems 11-16 de 16
Representing Integer Sequences Using Piecewise-Affine Loops
(MDPI, 2021)
[Abstract] A formal, high-level representation of programs is typically needed for static and dynamic analyses performed by compilers. However, the source code of target applications is not always available in an analyzable ...
Failure Avoidance in MPI Applications Using an Application-Level Approach
(Oxford University Press, 2014)
[Abstract] Execution times of large-scale computational science and engineering parallel applications are usually longer than the mean-time-between-failures. For this reason, hardware failures must be tolerated by the ...
CPPC: a compiler‐assisted tool for portable checkpointing of message‐passing applications
(John Wiley & Sons Ltd., 2010-11-19)
[Abstract] With the evolution of high‐performance computing toward heterogeneous, massively parallel systems, parallel applications have developed new checkpoint and restart necessities. Whether due to a failure in the ...
Compiler-Assisted Checkpointing of Parallel Codes: The Cetus and LLVM Experience
(Springer New York LLC, 2013)
[Abstract] With the evolution of high-performance computing, parallel applications have developed an increasing necessity for fault tolerance, most commonly provided by checkpoint and restart techniques. Checkpointing tools ...
Extending an Application-Level Checkpointing Tool to Provide Fault Tolerance Support to OpenMP Applications
(Technische Universitaet Graz * Institut fuer Informationssysteme und Computer Medien,Graz University of Technology, Institute for Information Systems and Computer Media, 2014-09)
[Abstract] Despite the increasing popularity of shared-memory systems, there is a lack of tools for providing fault tolerance support to shared-memory applications. CPPC (ComPiler for Portable Checkpointing) is an ...
Truncated SIMD Multiplier Architecture for Approximate Computing in Low-Power Programmable Processors
(Institute of Electrical and Electronics Engineers, 2019)
[Abstract]: Approximate computing has been exploited for many years in application-specific architectures. Recently, it has also been proposed for low-power programmable processors. However, this poses some challenges as, ...